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ics8431cm-11 www.icst.com/products/hiperclocks.html rev. a july 11, 2001 1

ICS8431-11 255mh z , l ow j itter , lvpecl f requency s ynthesizer g eneral d escription the ICS8431-11 is a general purpose clock frequency synthesizer for ia64/32 application and a member of the hiperclocks? family of high performance clock solutions from ics. the vco operates at a frequency range of 190mhz to 510mhz providing an output frequency range of 95mhz to 255mhz. the output frequency can be programmed using the parallel interface, m0 thru m8, to the configuration logic. spread spectrum clocking is programmed via the control inputs ssc_ctl0 and ssc_ctl1. programmable features of the ICS8431-11 support four operational modes. the four modes are spread spectrum clocking (ssc), non-spread spectrum clock and two test modes which are controlled by the ssc_ctl[1:0] pins. un- like other synthesizers, the ICS8431-11 can immediately change spread-spectrum operation without having to reset the device. in ssc mode, the output clock is modulated in order to achieve a reduction in emi. in one of the pll bypass test modes, the pll is disconnected as the source to the differential output allowing an external source to be connnected to the test_i/o pin. this is useful for in- circuit testing and allows the differential output to be driven at a lower frequency throughout the system clock tree. in the other pll bypass mode, the oscillator divider is used as the source to both the m and the fout divide by 2. this is useful for characterizing the oscillator and internal dividers. xtal1 xtal2 m0:m8 fout nfout 16 test_i/o osc vco 2 phase detector m ssc control logic configuration logic np_load ssc_ctl0 f eatures ? fully integrated pll ? differential 3.3v lvpecl output ? programmable pll loop divider for generating a variety of output frequencies. ? crystal oscillator interface ? spread spectrum clocking (ssc) fixed at 1/2% modulation for environments requiring ultra low emi ? typical rms cycle-to-cycle jitter 2.6 ps ? lvttl / lvcmos control inputs ? pll bypass modes supporting in-circuit testing and on-chip functional block characterization ? 3.3v supply voltage ? 28 lead soic ? 0 c to 85 c ambient operating temperature b lock d iagram p in a ssignment ssc_ctl1 m0 m1 m2 m3 m4 m5 m6 m7 m8 ssc_ctl0 ssc_ctl1 vee test_i/o vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 np_load vddi xtal2 xtal1 nc nc vdda vee mr nc vddo fout nfout vee ICS8431-11 28-lead soic m package to p vi e w hiperclocks ? ,&6
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ICS8431-11 255mh z , l ow j itter , lvpecl f requency s ynthesizer t able 1. p in d escriptions t able 2. p in c haracteristics r e b m u ne m a ne p y tn o i t p i r c s e d 5 - 16 m - 0 mt u p n in w o d l l u p f o n o i t s i s n a r t h g i h - o t - w o l n o d e h c t a l a t a d . s t u p n i r e d i v i d m . s l e v e l e c a f r e t n i s n i p l t t v l / s o m c v l . t u p n i d a o l _ p n 8 - 68 m - 7 mt u p n ip u l l u p f o n o i t s i s n a r t h g i h - o t - w o l n o d e h c t a l a t a d . s t u p n i r e d i v i d m . s l e v e l e c a f r e t n i s n i p l t t v l / s o m c v l . t u p n i d a o l _ p n 1 1 , 0 1 , 0 l t c c s s 1 l t c c s s t u p n ip u l l u p. s l e v e l e c a f r e t n i s o m c v l / l t t v l . s n i p l o r t n o c c c s 2 1e e vr e w o p. t u p t u o t s e t d n a e r o c r o f n i p d n u o r g 3 1o / i t s e t / t u p n i t u p t u o . e d o m s s a p y b l l p n i t u p n i s a d e m m a r g o r p 4 1d d vr e w o p. t u p t u o t s e t d n a e r o c r o f n i p y l p p u s r e w o p 5 1e e vr e w o p. t u p t u o r o f n i p d n u o r g 7 1 , 6 1t u o f , t u o f nt u p t u o . r e z i s e h t n y s e h t r o f s r e v i r d t u p t u o n i a m e r a s t u p t u o l a i t n e r e f f i d e s e h t l c e p v l d e c n e r e f e r e v i t i s o p d e t a n i m r e t h t i w e l b i t a p m o c e r a y e h t . c i g o l 8 1o d d vr e w o p. t u p t u o r o f n i p y l p p u s r e w o p 4 2 , 3 2 , 9 1c nd e s u n u. n o i t c e n n o c o n 0 2r mt u p n in w o d l l u p. w o l t u o f s e c r o f . r e t n u o c m t e s e r 1 2e e vr e w o p. n i p d n u o r g 2 2a d d vr e w o p. n i p y l p p u s r e w o p l l p 6 2 , 5 22 l a t x , 1 l a t xt u p n i. t u p n i r o t a l l i c s o l a t s y r c 7 2i d d vr e w o p. e r o c r o f n i p y l p p u s r e w o p 8 2d a o l _ p nt u p n in w o d l l u p. s l e v e l e c a f r e t n i s o m c v l / l t t v l . t u p n i e l b a n e h c t a l r e d i v i d m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n i ce c n a t i c a p a c n i p t u p n i 4f p p u l l u p rr o t s i s e r p u l l u p t u p n i 1 5k ? n w o d l l u p rr o t s i s e r n w o d l l u p t u p n i 1 5k ?
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ICS8431-11 255mh z , l ow j itter , lvpecl f requency s ynthesizer t able 3a. ssc c ontrol i nput f unction t able t able 3b. p rogrammable vco f requency f unction t able (note 1) s t u p n i o / i _ t s e t e c r u o s c s s s t u p t u o s e d o m l a n o i t a r e p o 1 l t c _ c s s0 l t c _ c s s , t u o f t u o f n o / i _ t s e t 00 l a n r e t n id e l b a s i dl a t x f 2 3 l a t x f 6 1 m n d n a m , r o t a l l i c s o , r o t a l l i c s o ; s s a p y b l l p 1 e t o n . e d o m t s e t s r e d i v i d 01l l pd e l b a n e m x l a t x f 2 3 z - i ht n e c r e p ? = r o t c a f n o i t a l u d o m ; c s s t l u a f e d 10 l a n r e t x ed e l b a s i dk l c t s e tt u p n i , e d o m s s a p y b l l p z h m 1 ( k l c t s e t 1 e t o n ; ) z h m 0 0 2 11 l l pd e l b a s i d m x l a t x f 2 3 z - i hn o i t a l u d o m c s s o n . n o i t a z i r e t c a r a h c d n a g u b e d e s u o h n i r o f d e s u : 1 e t o n y c n e u q e r f o c v ) z h m ( t n u o c m 6 5 28 2 14 62 36 18421 8 m7 m6 m5 m4 m3 m2 m1 m0 m 0 9 10 9 1 0 10 111110 1 9 11 9 1 0 10 111111 2 9 12 9 1 0 11000000 3 9 13 9 1 0 1100000 1 8 0 58 0 5 111111100 9 0 59 0 5 11111110 1 0 1 50 1 5 111111110 . l a t s y r c z h m 6 1 a s e m u s s a : 1 e t o n
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ICS8431-11 255mh z , l ow j itter , lvpecl f requency s ynthesizer a bsolute m aximum r atings supply voltage 4.6v inputs -0.5v to vdd + 0.5v outputs -0.5v to vddo + 0.5v ambient operating temperature 0 c to 85 c storage temperature -65 c to 150 c stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of product at these condition or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. t able 4b. lvcmos / lvttl dc c haracteristics , vdd = vdda = vddi = vddo = 3.3v5%, t a = 0 c to 85 c t able 4c. lvpecl dc c haracteristics , vdd = vdda = vddi = vddo = 3.3v5%, t a = 0 c to 85 c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u h o v1 e t o n ; e g a t l o v h g i h t u p t u o 8 2 . 1 - o d d v8 9 . 0 - o d d vv l o ve g a t l o v w o l t u p t u o1 e t o n ;0 . 2 - o d d v7 . 1 - o d d vv g n i w s vg n i w s e g a t l o v t u p t u o k a e p - o t - k a e p0 0 60 0 70 5 8v m 0 5 h t i w d e t a n i m r e t t u p t u o : 1 e t o n ? . v 2 - o d d v o t t able 4a. p ower s upply dc c haracteristics , vdd = vdda = vddi = vddo = 3.3v5%, t a = 0 c to 85 c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u h i ve g a t l o v h g i h t u p n i , 0 l t c _ c s s , 8 m : 0 m , r m , 1 l t c _ c s s d a o l _ p n , o / i _ t s e t v 5 3 1 . 3 d d v v 5 6 4 . 32 3 . 0 + d d vv l i ve g a t l o v w o l t u p n i , 0 l t c _ c s s , 8 m : 0 m , r m , 1 l t c _ c s s d a o l _ p n , o / i _ t s e t v 5 3 1 . 3 d d v v 5 6 4 . 33 . 0 -8 . 0v h i it n e r r u c h g i h t u p n i , 0 l t c _ c s s , 8 m , 7 m o i _ t s e t , 1 l t c _ c s s v 5 6 4 . 3 = n i v = d d v5a , 6 m : 0 m r m , d a o l _ p n v 5 6 4 . 3 = n i v = d d v0 5 1a l i it n e r r u c w o l t u p n i , 0 l t c _ c s s , 8 m , 7 m o i _ t s e t , 1 l t c _ c s s v 0 = n i v , v 5 6 4 . 3 = d d v0 5 1 -a , 6 m : 0 m r m , d a o l _ p n v 0 = n i v , v 5 6 4 . 3 = d d v5 -a l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u d d ve g a t l o v y l p p u s r e w o p 5 3 1 . 33 . 35 6 4 . 3v o d d ve g a t l o v y l p p u s r e w o p t u p t u o 5 3 1 . 33 . 35 6 4 . 3v a d d ve g a t l o v y l p p u s r e w o p g o l a n a 5 3 1 . 33 . 35 6 4 . 3v i d d ve g a t l o v y l p p u s r e w o p t u p n i 5 3 1 . 33 . 35 6 4 . 3v e e i 0 4 1a m
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ICS8431-11 255mh z , l ow j itter , lvpecl f requency s ynthesizer t able 6. ac c haracteristics , vdd = vdda = vddi = vddo = 3.3v5%, t a = 0 c to 85 c, 16mh z c rystal t able 5. c rystal c haracteristics r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u f y c n e u q e r f 0 . 6 1z h m e c n a r e l o t y c n e u q e r f 0 5 -0 5 +m p p y t i l i b a t s y c n e u q e r f 0 0 1 -0 0 1 +m p p l e v e l e v i r d 0 0 1w ) r s e ( e c n a t s i s e r s e i r e s t n e l a v i u q e 0 5 ? e c n a t i c a p a c t n u h s 37f p e c n a t i c a p a c d a o l 0 18 12 3f p e c n a t c u d n i n i p s e i r e s 37h n e g n a r e r u t a r e p m e t g n i t a r e p o 00 7c g n i g ac 5 2 @ r a e y r e p5 -5 +m p p l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u e v a f4 e t o n ; y c n e u q e r f t u p t u o e g a r e v a 0 5 7 -0 5 7 +m p p t j) c c ( t i 2 e t o n ; r e t t i j e l c y c - o t - e l c y c z h m 0 0 2 = t u o f8 10 3s p 5 3s p c d o; e l c y c y t u d t u p t u o2 e t o n7 43 5% r t2 , 1 e t o n ; e m i t e s i r t u p t u o% 0 8 o t % 0 20 0 30 5 40 0 6s p f t2 , 1 e t o n ; e m i t l l a f t u p t u o% 0 8 o t % 0 20 0 30 5 40 0 6s p l a t x f3 e t o n ; e g n a r t u p n i l a t s y r c4 16 10 2z h m m f ; y c n e u q e r f n o i t a l u d o m c s s 2 , 1 e t o n 0 33 3 . 3 3z h k f m f ; r o t c a f n o i t a l u d o m c s s 2 , 1 e t o n 4 . 06 . 0% d e r c s s; n o i t c u d e r l a r t c e p s2 , 1 e t o n70 1b d e l b a t s tt u p t u o k c o l c e l b a t s o t p u - r e w o p 0 1s m . d e l b a n e g n i k c o l c m u r t c e p s d a e r p s : 1 e t o n 0 5 h t i w d e t a n i m r e t s t u p t u o : 2 e t o n ? . v 2 - o d d v o t . e g n a r g n i t a r e p o o c v e h t n i h t i w d i l a v y l n o : 3 e t o n . s t n e n o p m o c l a t s y r c l a n r e t x e t u o h t i w : 4 e t o n t j. s n o i t i n i f e d 5 6 d s e j c e d e j o t m r o f n o c c d o , f t , r t , ) c c ( t i
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ICS8431-11 255mh z , l ow j itter , lvpecl f requency s ynthesizer p arameter m easurement i nformation ? ? ? ? f igure 2 ? c ycle - to -c ycle j itter fout t jit(cc) = t cycle n ? t cycle n+1 nfout t cycle n t cycle n+1 ? ? ? ? ? ? clock inputs and outputs 80% 20% 80% 20% t rise t fall vswing f igure 1 ? i nput and o utput s lew r ates f igure 3 ? odc & t period pulse width (t pw ) t period t pw t period odc = nfout fout
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ICS8431-11 255mh z , l ow j itter , lvpecl f requency s ynthesizer f unctional d escription the ICS8431-11 features a fully integrated pll and therefore requires no external components for setting the loop bandwidth. a 16mhz series-resonant, fundamental crystal is used as the input to the on-chip oscillator. the output of the oscillator is di vided by 16 prior to the phase detector. with a 16mhz crystal this provides a 1mhz reference frequency. the vco of the pll operates over a range of 190 to 510mhz. the output of the loop divider is also applied to the phase detector. the phase detector and the loop filter force the vco output frequency to be m times the reference frequency by adjusting the vco control voltage. note that for some values of m (either too high or too low) the pll will not achieve lock. the output of t he vco is scaled by a divider prior to being sent to the lvpecl output buffer. the divider provides a 50% output duty cycle. the programmable features of the ICS8431-11 support four output operational modes and a programmable pll loop divider. the four output operational modes are spread spectrum clocking (ssc), non-spread spectrum clock and two test modes and are controlled by the ssc_ctl[1:0] pins. the pll loop divider or m divider is programmed by using inputs m0 through m8. while the np_load input is held low, the data present at m0:m8 is transparent to the m-divider. on the low-to-high transition of np_load, the m0:m8 data is latched into the m-divider and any further changes at the m0:m8 inputs will not be seen by the m-divider until the next low transition on np_load. the relationship between the vco frequency, the crystal frequency and the loop counter/divider is defined as follows: the m count and the required values of m0:m8 for programming the vco are shown in table 3b , programmable vco frequency function table. the frequency out is defined as follows: for the ICS8431-11, the output divider equals 2. valid m values for which the pll will achieve lock are defined as 190 m 510. 16 m fvco = fxtal x 2 fout = fvco = 32 fxtal x m
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ICS8431-11 255mh z , l ow j itter , lvpecl f requency s ynthesizer c rystal i nput and o scillator i nterface the ICS8431-11 features an internal oscillator that uses an external quartz crystal as the source of its reference frequency. a 16mhz crystal divided by 16 before being sent to the phase detector provides the reference frequency. the oscillator is a series resonant, multi-vibrator type design. this design provides better stability and eliminates the need for large on chip capacitors. though a series resonant crystal is preferred, a parallel resonant crystal can be used. a parallel resonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified. a few hundred ppm translates to khz inaccuracy. in general computing applications this level of inaccuracy is irrelevant. if better ppm accuracy is required, an external capacitor can be added to a parallel resonant crystal in series to pin 25. figure 1a shows how to interface with a crystal. figures 1a, 1b, and 1c show various crystal parameters which are recommended only as guidelines. figure 1a shows how to interface a capacitor with a parallel resonant crystal. figure 1b shows the capacitor value needed for the optimum ppm performance over various parallel resonant crystals. figure 1c shows the recommended tuning capacitance for a various parallel resonant crystal. f igure 1a. c rystal i nterface optional xtal2 (pin 26, soic) xtal1 (pin 25, soic) ICS8431-11 ? f igure 1b. recommended tuning capacitance for various parallel resonant crystals. f igure 1c. recommended tuning capacitance for various parallel resonant crystal. 14.318 15.000 16.667 24.000 19.440 20.000 0 10 20 30 40 50 60 14 15 16 17 18 19 20 21 22 23 24 25 crystal frequency (mhz) series capacitor, c1 (pf) -100 -80 -60 -40 -20 0 20 40 60 80 100 0 102030405060 series capacitor, c1 (pf) frequency accuracy (ppm) 19.44mhz 16mhz 15.00mhz
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ICS8431-11 255mh z , l ow j itter , lvpecl f requency s ynthesizer s pread s pectrum spread-spectrum clocking is a frequency modulation tech- nique for emi reduction. when spread-spectrum is enabled, a 30khz triangle waveform is used with 0.5% down-spread (+0.0% / -0.5%) from the nominal 200mhz clock frequency. an example of a triangle frequency modulation profile is shown in figure 2 below. the ramp profile can be expressed as: fnom = nominal clock frequency in spread off mode (200mhz with 16mhz in) fm = nominal modulation frequency (30khz) = modulation factor (0.5% down spread) (1 - ) fnom + 2 fm x x fnom x t when 0 < t < , (1 - ) fnom - 2 fm x x fnom x t when < t < 1 2 fm 1 2 fm 1 fm the ICS8431-11 triangle modulation frequency deviation will not exceed 0.6% down-spread from the nominal clock fre- quency (+0.0% / -0.5%). an example of the amount of down spread relative to the nominal clock frequency can be seen in the frequency domain, as shown in figure 3. the ratio of this width to the fundamental frequency is typically 0.4%, and will not exceed 0.6%. the resulting spectral reduction will be greater than 7db, as shown in figure 3. it is important to note the ICS8431-11 7db minimum spectral reduction is the com- ponent-specific emi reduction, and will not necessarily be the same as the system emi reduction. p ower s upply f iltering t echniques as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ICS8431-11 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. vdd, vddi, vdda, and vddo should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, better power supply isolation is required. figure 4 illustrates how a 10 ? along with a 10 f and a .01 f bypass capacitor should be connected to each power supply pin. f igure 3. 200mh z c lock o utput in f requency d omain (a) s pread -s pectrum off (b) s pread -s pectrum on ? ? 10 dbm = .4% b a ? ? fnom (1 - ) fnom 0.5/fm 1/fm f igure 2. t riangle f requency m odulation f igure 4. p ower s upply f iltering 10 ? vdda 10 f .01 f 3.3v .01 f vdd
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ICS8431-11 255mh z , l ow j itter , lvpecl f requency s ynthesizer t ermination for pecl o utputs the clock layout topology shown below is typical for ia64/32 platforms. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/pecl compatible outputs. therefore, terminat- ing resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to f igure 5b. lvpecl o utput t ermination 3.3v fout fin 5 2 z o z o 5 2 z o 3 2 z o 3 2 z o = 50 ? z o = 50 ? z o = 50 ? z o = 50 ? f igure 5a. lvpecl o utput t ermination rtt = 1 (voh + vol / vcc ? 2) ? 2 z o z o = 50 ? z o = 50 ? 50 ? 50 ? rtt vcc-2v fin fout ? z o = 50 ? z o = 50 ? f igure 6a. r ecommended s chematic l ayout drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and mini- mize signal distortion. there are a few simple termination schemes. figures 5a and 5b show two different layouts which are recommended only as guidelines. other suitable clock lay- outs may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. l ayout g uideline the schematic of the ICS8431-11 layout example used in this layout guideline is shown in figure 6a. the ICS8431-11 recommended pcb board layout for this example is shown in figure 6b. this layout example is used as a general guideline. the layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stacking of the p.c. board. vdd r1 125 r5 10 r1 50 r3 125 c3 0.01uf r4 84 in+ in- tl1 zo = 50 ohm vdda r3 50 x1 r2 84 vdd u1 8431-11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 28 27 26 25 m0 m1 m2 m3 m4 m5 m6 m7 m8 ssc_ctl0 ssc_ctl1 gnd test_io vdd gnd nfout fout vddo nc nc nc vdda nc nc np_load vddi xtal1 xtal2 termination a in- c6 0.01uf in+ c1 0.1uf c4 10uf r2 50 vdd tl2 zo = 50 ohm vdd0 termination b (not shown in the layout) c2 0.1uf
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ICS8431-11 255mh z , l ow j itter , lvpecl f requency s ynthesizer f igure 6b. pcb b oard l ayout f or ICS8431-11 the following component footprints are used in this layout example: all the resistors and capacitors are size 0603. p ower and g rounding place the decoupling capacitors c1, c2 and c3, c4, c5, c6 as close as possible to the power pins. if space allows, placing the decoupling capacitor at the component side is preferred. this can reduce unwanted inductance between the decoupling capacitor and the power pin generated by the via. maximize the pad size of the power (ground) at the decoupling capacitor. maximize the number of vias between power (ground) and the pads. this can reduce the inductance between the power (ground) plane and the component power (ground) pins. if vdda shares the same power supply with vdd, insert the rc filter r5, c3, and c4 in between. place this rc filter as close to the vdda as possible. c lock t races and t ermination the component placements, locations and orientations should be arranged to achieve the best clock signal quality. poor clock signal quality can degrade the system performance or cause system failure. in the synchronous high-speed digital system, the clock signal is less tolerable to poor signal quality than other signals. any ringing on the rising or falling edge or excessive ring back can cause system failure. the trace shape and the trace delay might be restricted by the available space on the board and the component location. while routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signals traces. the traces with 50 ? transmission lines tl1 and tl2 at fout and nfout should have equal delay and run ad- jacent to each other. avoid sharp angles on the clock trace. sharp angle turns cause the characteristic impedance to change on the transmission lines. keep the clock trace on same layer. whenever possible, avoid any vias on the clock traces. any via on the trace can affect the trace characteristic impedance and hence degrade signal quality. to prevent cross talk, avoid routing other signal traces in parallel with the clock traces. if running parallel traces is unavoidable, allow more space between the clock trace and the other signal trace. make sure no other signal trace is routed between the clock trace pair. the matching termination resistors r1, r2, r3 and r4 should be located as close to the receiver input pins as possible. other termi- nation scheme can also be used but is not shown in this example. c rystal the crystal x1 should be located as close as possible to the pins 26 (xtal1) and 25 (xtal2). the trace length between the x1 and u1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. other signal traces should not be routed near the crystal traces. gnd x1 r5 c6 tl2 (50 ohm) vdd signals c4 u1 ICS8431-11 r2 tl1 (50 ohm) c2 r3 via r1 c1 close to the input pins of the receiver in- c3 r4 in+
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ICS8431-11 255mh z , l ow j itter , lvpecl f requency s ynthesizer p ackage o utline - m s uffix t able 7. p ackage d imensions r eference d ocument : jedec p ublication 95, ms-013, mo-119 d e h .10 (.004) seating plane e a n a1 a2 b c l 14 15 28 1 h x 45 o l o b m y s s r e t e m i l l i ms e h c n i n i mx a mn i mx a m n8 2 a- -5 6 . 2- -4 0 1 . 0 1 a0 1 . 0- -0 4 0 0 . 0- - 2 a5 0 . 25 5 . 21 8 0 . 00 0 1 . 0 b3 3 . 01 5 . 03 1 0 . 00 2 0 . 0 c8 1 . 02 3 . 07 0 0 . 03 1 0 . 0 d0 7 . 7 10 4 . 8 17 9 6 . 04 2 7 . 0 e0 4 . 70 6 . 71 9 2 . 09 9 2 . 0 ec i s a b 7 2 . 1c i s a b 0 5 0 . 0 h0 0 . 0 15 6 . 0 14 9 3 . 09 1 4 . 0 h5 2 . 05 7 . 00 1 0 . 09 2 0 . 0 l0 4 . 07 2 . 16 1 0 . 00 5 0 . 0 0 8 0 8
ics8431cm-11 www.icst.com/products/hiperclocks.html rev. a july 11, 2001 13

ICS8431-11 255mh z , l ow j itter , lvpecl f requency s ynthesizer t able 8. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pt n u o ce r u t a r e p m e t 1 1 - m c 1 3 4 8 s c i1 1 - m c 1 3 4 8 s c ic i o s d a e l 8 2e b u t r e p 6 2c 0 7 o t c 0 t 1 1 - m c 1 3 4 8 s c i1 1 - m c 1 3 4 8 s c il e e r d n a e p a t n o c i o s d a e l 8 20 0 0 1c 0 7 o t c 0

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